Whether Motorola's own roadmap will move this way isn't known, but given both companies will be starting again from the same base - call it Apollo - they may not diverge too far this time.

It's a tad pie-in-the-sky, but it doesn't sound all that far off IBM's Cell project, announced recently with Sony and Toshiba. Enhanced PowerPC Architecture', which extends the multi-core approach to a complex system in which cores operate in parallel on a switched version of CoreConnect and talk to the outside world via a 'new high-speed interface'. Looking beyond this generation, to the 2GHz+ parts, IBM talks about an 'ultrascalar. For its part, IBM seems a recent convert - it only joined the RapidIO Trade Association at the end of April. MaxBus may simply be Motorola's name for RapidIO, or it may be the basis for the standard, we're not sure - perhaps someone from the chip company would care to put us in the picture. RapidIO, meanwhile, appears to be a replacement for Motorola's 128-bit MaxBus, originally designed for the G4 but never implemented to its fullest degree.

IBM already uses SOI, and while Motorola doesn't, it is expected to with Apollo. IBM's version is planned to be produced at 0.13-0.10 micron, using low-k dielectric and silicon-on-insulator technology. Whatever, IBM's next-generation architecture sounds suspiciously like Motorola's own evolution of the technology, codenamed Apollo and G5. We speculated at the time that IBM might come nosing around AltiVec, and it looks like we were right. We suspect its attitude changed when it won the contract to develop a PowerPC chip for Nintendo's next-generation Gamecube 3D games console - a perfect application for AltiVec if there ever was one.

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